Three-dimensional (3D) integration of various materials on top of bulk silicon could be the best answer for cost-effectively marrying optical devices with electronics. A*STAR researchers have used this approach to create a photodetector system for optical communications on a silicon chip ("Three-dimensional (3D) monolithically integrated photodetector and WDM receiver based on bulk silicon wafer"). 
A germanium photodetector integrated on a silicon bulk wafer. (© Optical Society of America) As computers become increasingly powerful, there is a need to find elegant ways to combine electronics and high-speed optical interconnect technology to meet the growing demand for ever faster data processing and communication. “We believe that, in the future of on-chip and chip-to-chip communication, opto-electric integrated circuits on silicon will be a key technology to realize high-speed, low-power and low-cost chips,” explains Junfeng Song from the A*STAR Institute of Microelectronics. To date, most attempts to make hybrid electronic-optical silicon chips have relied on silicon-on-insulator (SOI) technology in which an insulating layer of silicon dioxide is formed on a silicon wafer. While this approach works well, it has the disadvantage of being very expensive — SOI wafers cost about ten times more than bulk silicon wafers. SOI wafers also suffer from poor thermal conductivity, making it difficult to dissipate heat from devices. The team instead decided to explore the use of conventional bulk silicon wafers, which are a natural platform for microelectronics, but then fabricate optical devices in layers integrated on top of the wafers, resulting in a 3D design. Song and co-workers demonstrated this concept by fabricating an integrated photodetector system. A germanium detector was built directly on top of a silicon wafer (see image) and fed with an optical waveguide and grating coupler formed in silicon nitride. The researchers tested the detector and found it was capable of handling data at speeds of 10 gigabits per second per wavelength channel. The team is confident that this can be pushed to much higher speeds. “In the current device, the three-decibel bandwidth is small but by employing an electronic amplifier we can already get 20 gigabits per second rather easily,” explains Song. “I don’t think that the data rate has any physical limit, so it should be possible to achieve 50 gigabits per second or higher.” According to Song, the next challenge is to make more sophisticated integrated systems featuring more optical devices and more electronics. Possibilities include adding optical modulators, variable optical attenuators, optical switches, electronic amplifiers and electronic drivers to the chip circuitry. Other plans are to experiment with using alternative materials on top of the silicon, such as aluminum nitride, which has electro-optic properties and could bring new functionality.
A germanium photodetector integrated on a silicon bulk wafer. (© Optical Society of America) As computers become increasingly powerful, there is a need to find elegant ways to combine electronics and high-speed optical interconnect technology to meet the growing demand for ever faster data processing and communication. “We believe that, in the future of on-chip and chip-to-chip communication, opto-electric integrated circuits on silicon will be a key technology to realize high-speed, low-power and low-cost chips,” explains Junfeng Song from the A*STAR Institute of Microelectronics. To date, most attempts to make hybrid electronic-optical silicon chips have relied on silicon-on-insulator (SOI) technology in which an insulating layer of silicon dioxide is formed on a silicon wafer. While this approach works well, it has the disadvantage of being very expensive — SOI wafers cost about ten times more than bulk silicon wafers. SOI wafers also suffer from poor thermal conductivity, making it difficult to dissipate heat from devices. The team instead decided to explore the use of conventional bulk silicon wafers, which are a natural platform for microelectronics, but then fabricate optical devices in layers integrated on top of the wafers, resulting in a 3D design. Song and co-workers demonstrated this concept by fabricating an integrated photodetector system. A germanium detector was built directly on top of a silicon wafer (see image) and fed with an optical waveguide and grating coupler formed in silicon nitride. The researchers tested the detector and found it was capable of handling data at speeds of 10 gigabits per second per wavelength channel. The team is confident that this can be pushed to much higher speeds. “In the current device, the three-decibel bandwidth is small but by employing an electronic amplifier we can already get 20 gigabits per second rather easily,” explains Song. “I don’t think that the data rate has any physical limit, so it should be possible to achieve 50 gigabits per second or higher.” According to Song, the next challenge is to make more sophisticated integrated systems featuring more optical devices and more electronics. Possibilities include adding optical modulators, variable optical attenuators, optical switches, electronic amplifiers and electronic drivers to the chip circuitry. Other plans are to experiment with using alternative materials on top of the silicon, such as aluminum nitride, which has electro-optic properties and could bring new functionality.
Superhydrophobic surfaces, which strongly repel water, are promising for many applications. Surfaces that strongly repel water, known as superhydrophobic surfaces, are important for many industrial applications as well as self-cleaning, defrosting and anti-icing surfaces. Scientists have discovered that inherently water repellent surfaces can be made much more water repellent by patterning them with micro- or nanoscale structures. On such surfaces, water droplets can either be suspended across neighboring protrusions or impaled between them. The transition between these two states has previously been explored experimentally and theoretically. Furthermore, the effect of microstructures on vapor condensation has been studied experimentally, but there have been few computational studies of how droplets initially form by condensation from vapor. Now, Weiqing Ren from the A*STAR Institute of High Performance Computing and Yunzhi Li of the National University of Singapore have systematically analyzed how micropillars on a hydrophobic surface affect the condensation of water vapor. To do this, they used a powerful computational technique known as the string method, which Ren developed in a previous study. Ren and Li used the technique to investigate the effect of parameters such as the height and spacing of the micropillars and the supersaturation and intrinsic wettability of the surface on the condensation process. They discovered that both the pathway and configuration of the initial nucleus from which droplets form — known as the critical nucleus — depends on the geometry of the surface patterns. In particular, the scientists found that for tall, closely spaced pillars on a surface with a low supersaturation and low wettability, the critical nucleus prefers the suspended state, whereas for the opposite case it prefers the impaled state. By generating a phase diagram, they could determine the critical values of the geometrical parameters at which the configuration of the critical nucleus changes from the suspended state to the impaled state. These results provide “insights into the effect of surface structure on condensation,” explains Ren, “and a quantitative basis for designing surfaces optimized to either inhibit or enhance condensation in engineered systems.” In the future, the researchers intend to study how fluid flow affects nucleation and the wetting transition on patterned surfaces.
This shows how the surface carrier lifetime of anatase and rutile TiO